The term “silicon-on-insulator” or “SOI” generally refers to a composite semiconductor article or product consisting of a thin layer of silicon attached to and supported by an insulating layer or substrate, and also to technologies based on such products. In view of their role as starting materials for subsequent processing, such articles are often referred to in the art as “substrates” and are typically provided in standard wafer form so that they can be used with standard semiconductor manufacturing equipment and processes.
SOI substrates can be manufactured by a variety of different methods, including the direct deposition or epitaxial growth of a thin layer of silicon on a compatible electrically insulating (e.g., sapphire) substrate, the in situ formation of a buried layer of SiO2 under a single-crystal silicon layer by implanting oxygen into a bulk silicon wafer in accordance with the SIMOX (separation by implantation of oxygen) method, and methods based on wafer bonding, including BE-SOI (bond-and-etch-back SOI), and layer transfer methods such as the Smart-Cut™ method described in U.S. Pat. No. 5,374,564. Although SOI wafers are more expensive than monolithic or bulk silicon wafers, they provide a number of technical advantages, particularly when high speed electronic devices are formed in the thin silicon layer, including reduced junction capacitance, low standby power, radiation tolerance, and freedom from latchup.
The standard form of SOI substrate is a ‘sandwich’ structure wherein a buried silicon dioxide (SiO2) layer provides the desired electrical isolation between the thin silicon layer and a thick supporting silicon base or substrate. However, this buried dielectric layer is also a barrier to heat flow from the devices fabricated in the silicon layer, due to the relatively poor thermal conductivity of SiO2. Consequently, the temperature of the channel of a MOSFET device formed in the thin silicon layer inevitably increases during operation to temperatures that are substantially higher than the corresponding temperatures of an equivalent device formed in a bulk silicon wafer, thereby degrading the performance and possibly the lifetime of the device.
To address this issue, a number of researchers have fabricated SOI substrates in which a buried layer of aluminium nitride (AlN), rather than the conventional SiO2, is used as the insulating material. This arrangement greatly reduces the often severe self-heating problem of conventional SOL since the thermal conductivity of AlN is ˜100 times that of SiO2, (136 W/mK vs. 1.4 W/mK) and is roughly equal to that of silicon itself 145 W/mK. In addition, AlN has excellent thermal stability, high electrical resistance and a coefficient of thermal expansion close to that of silicon.
For example, as described in M. Zhu et. al., Formation of silicon-ion-aluminum nitride using ion-cut and theoretical investigation of self-heating effects, Materials Letters 59 (2005) 510-513, and in C. Men et. al., Fabrication of SOI structure with AlN film as buried insulator by Ion-Cut process, Applied Surface Science 199 (2002) 287-292, an AlN layer can be formed on a standard (100) silicon wafer by metal plasma immersion ion implantation deposition (Me-PIIID), or by ion beam enhanced deposition (IBED) with the electron beam evaporation of Al and simultaneous bombardment of nitrogen ion beam. Then the deposited film can be directly bonded to a standard (100) silicon wafer that has previously been implanted with high energy hydrogen ions to form a buried layer. The bonded wafers can then be heated to strengthen the bond between the wafers and to cause the surface layer of the implanted wafer to split off using an ion-cut or Smart-Cut™ method. The result is a silicon-on-aluminum nitride or ‘SOAN’ substrate.
Despite the promise of SOAN substrates, they have not progressed beyond the research phase and are not commercially available. The inventors of the present invention believe this is likely to be caused by poor bonding between the silicon and aluminum nitride surfaces, due not only to common factors such as surface roughness and wafer flatness, but also to inherent poor bonding strength between these two materials. The rather poor quality of the deposited AlN layer may also play a role.
It is desired to provide a silicon-on-insulator article and a method of forming a silicon-on-insulator article that alleviate one or more difficulties of the prior art, or that at least provide a useful alternative.